In recent years, the development of a transistor having a silicon on insulator (SOI) structure (or an SOI transistor) has been performed energetically from the point of view of its low electrical power consumption, its capability of being driven in a high speed, and the like. It is known that the complete isolation of elements of the SOI transistors from each other becomes easy owing to their SOI structures, and that it becomes possible to suppress software errors and latch-up peculiar to a CMOS transistor. Accordingly, since comparatively early times, considerations have been made on making the speed and the reliability of a CMOS transistor LSI higher by means of an SOI structure having an Si active layer being abut 500 nm.
If an SOI transistor is in the condition in which almost all of its Si active layer is depleted (or a complete depletion type SOI transistor) by the control of the surface Si layer of its SOI to be further thinner to be approximately 100 nm or less, and by controlling of the impurity concentration of its channel to be comparatively low, the SOI transistor may have further optimized characteristics such as the steep rising of a drain current in a subthreshold region and the like as well as the decrease of the capacities of its diffusion layers. Consequently, people have recently begun to expect the application of the complete depletion type SOI transistor in low electrical power consumption LSI regarded as a requirement for upcoming portable equipment and the like.
However, it has become necessary for the complete depletion type SOI transistor to have a thinner S01 film according to the reduction according to design rule (a single gate type SOI is generally required to have the thickness of a channel SOI film of a tenth of a finished gate length or less). Consequently, the following problems have become conspicuous.
In other words, as for the thickness of an SOI film required for next generation fine LSI's, a further thinner SOI layer is required for keeping the reduction of the gate length of the complete depletion type SOI transistor if it is attempted at suppressing a short channel effect only by the formation of the thickness of the SOI film to be thinner in the complete deletion type SOI.
For example, Hon-Sum Philip Wong, et al. reported calculation results by means of a device simulator in 1998 IEEE, IEDM 98, pp. 407-410. According to the report, the roll-off of Vth cannot sufficiently be suppressed unless the thickness of the SOI film is 10 nm or less in case of a 0.1 μm generation transistor. However, the thickness is only a simulation result. If it is tried to make a device having such a thin thickness of a SOI film actually, the following problems occur on its process.
(1) Increase of Parasitic Resistance
(2) Deterioration of Controllability of Threshold Voltage (Vth)
(3) Problem of Contact Formation on Diffusion Layer
(4) Problem of decrease of mobility of carriers (quantum effect)
(5) Deterioration of crystallinity (or generation of aggregation of Si)
In other words, when an SOI layer becomes turns to an extremely thin film, even if silicides are formed, parasitic resistances cannot be decreased at a large extent even though the thickness of a metal film is made to be thick because a Si layer has a finite film thickness. Furthermore, if the thickness of an SOI film or a silicide film in a diffusion layer becomes extremely thin, it becomes very difficult to stop etching at the diffusion layer at the time of the working of an interlayer dielectric for forming a first contact.
In addition, if it is attempted at suppressing the short channel effect only by the formation of the SOI layer to be thinner, it becomes necessary to add, for example, selective epitaxial growth, the control of the work function of a gate electrode, and the like. On the other hand, the problems of the decrease of the mobility of carries owing to a quantum effect, the aggregation of Si, and the like are essential problems inherent to the material, and therefore their solution is very difficult.
In addition, if it is attempted at controlling the threshold value of a complete depletion type SOI transistor by means of the concentration of an impurity to be introduced into a channel, the threshold value is determined by the total amount of the introduced impurity. Consequently, because the total amount of the impurity changes in dependence of the thickness of the SOI film, the dispersion of the threshold value owing to the changes of the thickness of the SOI film becomes large.